This invention relates to microelectronic manufacturing methods and devices, and more particularly to silicon ingot manufacturing methods and silicon ingots and wafers manufactured thereby.
Integrated circuits are widely used in consumer and commercial applications. Integrated circuits are generally fabricated from monocrystalline silicon. As the integration density of integrated circuits continues to increase, it generally is of increasing importance to provide high-quality monocrystalline semiconductor material for integrated circuits. Integrated circuits are typically produced by fabricating a large ingot of monocrystalline silicon, slicing the ingot into wafers, performing numerous microelectronic fabrication processes on the wafers and then dicing the wafers into individual integrated circuits that are packaged. Because the purity and crystallinity of the silicon ingot can have a large impact on the performance of the ultimate integrated circuit devices that are fabricated therefrom, increased efforts have been made to fabricate ingots and wafers with reduced numbers of defects.
Conventional methods of manufacturing monocrystalline silicon ingots will now be described. An overview of these methods is provided in Chapter 1 of the textbook xe2x80x9cSilicon Processing for the VLSI Era, Volume 1, Process Technologyxe2x80x9d, by Wolf and Tauber, 1986, pp. 1-35, the disclosure of which is hereby incorporated herein by reference. In manufacturing monocrystalline silicon, electronic grade polysilicon is converted into a monocrystalline silicon ingot. Polycrystalline silicon such as quartzite is refined to produce electronic grade polycrystalline silicon. The refined electronic grade polycrystalline silicon is then grown into a single crystal ingot using the Czochralski (CZ) or Float Zone (FZ) technique. Since the present invention relates to manufacturing a silicon ingot using the CZ technique, this technique will now be described.
CZ growth involves crystalline solidification of atoms from a liquid phase at an interface. In particular, a crucible is loaded with a charge of electronic grade polycrystalline silicon and the charge is melted. A seed crystal of silicon of precise orientation tolerances is lowered into the molten silicon. The seed crystal is then withdrawn at a controlled rate in the axial direction. Both the seed crystal and the crucible are generally rotated during the pulling process, in opposite directions.
The initial pull rate is generally relatively rapid so that a thin neck of silicon is produced. Then, the melt temperature is reduced and stabilized so that the desired ingot diameter can be formed. This diameter is generally maintained by controlling the pull rate. The pulling continues until the charge is nearly exhausted, at which time a tail is formed.
FIG. 1 is a schematic diagram of a CZ puller. As shown in FIG. 1, the CZ puller 100 includes a furnace, a crystal pulling mechanism, an environment controller and a computer-based control system. The CZ furnace is generally referred to as a hot zone furnace. The hot zone furnace includes heating elements 102 and 104, an inner crucible 106 which may be made of quartz, an outer crucible 108 which may be made of graphite and a rotation shaft 110 that rotates in a first direction 112 as shown. A hot shield 114 may provide additional thermal distribution.
The crystal pulling mechanism includes a crystal pulling shaft 120 which may rotate in direction 122 opposite direction 112 as shown. Crystal pulling shaft 120 holds seed crystal 124, which is pulled from molten polysilicon charge 126 in crucible 106 to form ingot 128.
The ambient control system may include the chamber enclosure 140, a cooling port 132 and other flow controllers and vacuum exhaust systems that are not shown. A computer-based control system may be used to control the heating elements, puller and other electrical and mechanical elements.
In order to grow a monocrystalline silicon ingot, the seed crystal 124 is contacted to the molten silicon charge 126 and is gradually pulled in the axial direction (up). Cooling and solidification of the molten silicon charge 126 into monocrystalline silicon occurs at the interface 130 between the ingot 128 and the molten silicon 126.
Real silicon ingots differ from ideal monocrystalline ingots because they include imperfections or defects. These defects are undesirable in fabricating integrated circuit devices. These defects may be generally classified as point defects or agglomerates (three-dimensional defects). Point defects are of two general types: vacancy point defects and interstitial point defects. In a vacancy point defect, a silicon atom is missing from one of its normal positions in the silicon crystal lattice. This vacancy gives rise to a vacancy point defect. On the other hand, if an atom is found at a non-lattice site (interstitial site) in the silicon crystal, it gives rise to an interstitial point defect.
Point defects are generally formed at the interface 130 between the molten silicon 126 and the solid silicon 128. However, as the ingot 128 continues to be pulled, the portion that was at the interface begins to cool. During cooling, diffusion of vacancy point defects and interstitial point defects may cause defects to coalesce and form vacancy agglomerates or interstitial agglomerates. Agglomerates are three-dimensional (large) structures that arise due to coalescence of point defects. Interstitial agglomerates are also referred to as dislocation defects or D-defects. Agglomerates are also sometimes named by the technique that is used to detect these defects. Thus, vacancy agglomerates are sometimes referred to as Crystal-Originated Particles (COP), Laser Scattering Tomography (LST) defects or Flow Pattern Defects (FPD). Interstitial agglomerates are also known as Large Dislocation (L/D) agglomerates. A discussion of defects in monocrystalline silicon is provided in Chapter 2 of the above-mentioned textbook by Wolf and Tauber, the disclosure of which is hereby incorporated herein by reference.
It is known that many parameters may need to be controlled in order to grow a high purity ingot having low numbers of defects. For example, it is known to control the pull rate of the seed crystal and the temperature gradients in the hot zone structure. Voronkov""s Theory found that the ratio of V to G (referred to as V/G) can determine the point defect concentration in the ingot, where V is the pull rate of the ingot and G is the temperature gradient of the ingot-melt interface. Voronkov""s Theory is described in detail in xe2x80x9cThe Mechanism of Swirl Defects Formation in Siliconxe2x80x9d by Voronkov, Journal of Crystal Growth, Vol. 59, 1982, pp. 625-643.
An application of Voronkov""s Theory may be found in a publication by the present inventor et al. entitled xe2x80x9cEffect of Crystal Defects on Device Characteristicsxe2x80x9d, Proceedings of the Second International Symposium on Advanced Science and Technology of Silicon Material, Nov. 25-29, 1996, p. 519. At FIG. 15, reproduced herein as FIG. 2, a graphical illustration of vacancy and interstitial concentrations, as a function of V/G is shown. Voronkov""s Theory shows that the generation of vacancy/interstitial mixture in a wafer is determined by V/G. More particularly, for V/G ratios below a critical ratio, an interstitial rich ingot is formed, while for V/G ratios above the critical ratio, a vacancy rich ingot is formed.
Notwithstanding many theoretical investigations by physicists, material scientists and others, and many practical investigations by CZ puller manufacturers, there continues to be a need to reduce the defect density in monocrystalline silicon wafers. The ultimate need is for pure silicon wafers that are free of vacancy and interstitial agglomerates.
The present invention provides methods of manufacturing a silicon ingot in a hot zone furnace by pulling the ingot from a silicon melt in the hot zone furnace in an axial direction, at a pull rate profile of the ingot from the silicon melt in the hot zone furnace that is sufficiently high so as to prevent interstitial agglomerates but is sufficiently low so as to confine vacancy agglomerates to a vacancy rich region at the axis of the ingot. The ingot so pulled is sliced into a plurality of semi-pure wafers each having a vacancy rich region at the center thereof that includes vacancy agglomerates and a pure region between the vacancy rich region and the wafer edge that is free of vacancy agglomerates and interstitial agglomerates.
The present invention stems from the realization that agglomerates will form from point defects only if the point defect concentration exceeds a certain critical concentration. If the point defect concentration (vacancy or interstitial) can be maintained below this critical concentration, agglomerates will not form as the ingot is being pulled. In order to maintain point defect concentrations below critical point defect concentrations, the ratio of pull rate to temperature gradient at the ingot-melt interface (V/G) is confined (1) above a first critical ratio of pull rate to temperature gradient at the ingot-melt interface that must be maintained in order to prevent interstitial agglomerates and (2) below a second critical ratio of pull rate to temperature gradient at the ingot-melt interface that cannot be exceeded in order to confine vacancy agglomerates to a vacancy rich region at the center of the ingot. The pull rate profile is therefore adjusted to maintain the ratio of pull rate to temperature gradient above the first critical ratio and below the second critical ratio as the ingot is pulled from the silicon melt in the hot zone furnace.
According to another aspect of the present invention, the ingot is pulled from the silicon melt in the hot zone furnace at a pull rate profile of the ingot from the silicon melt in the hot zone furnace that is sufficiently high so as to prevent interstitial agglomerates, but is also sufficiently low as to prevent vacancy agglomerates. Accordingly, when this ingot is sliced into wafers, the wafers are pure silicon wafers that may include point defects but that are free of vacancy agglomerates and interstitial agglomerates.
According to this aspect of the invention, it has been determined that if the V/G ratio is confined to within a narrower range, both the point interstitial concentration and the point vacancy concentration can be maintained below the critical point defect concentrations that will form agglomerates. Thus, the entire ingot can be agglomerate free.
To form pure silicon, a first critical ratio of pull rate to temperature gradient at the ingot melt interface is determined, that must be maintained to prevent interstitial agglomerates. A second critical ratio of pull rate to temperature gradient at the ingot-melt interface that cannot be exceeded in order to prevent vacancy agglomerates is determined. A pull rate profile is then determined that maintains the ratio of pull rate to temperature gradient above the first critical ratio and below the second critical ratio as the ingot is pulled from the silicon melt in the hot zone surface.
In order to maintain the ratio of pull rate to temperature gradient at the ingot-melt interface between the two critical ratios, radial temperature gradients and axial temperature gradients are considered. In the radial direction, the temperature gradient across a wafer will generally vary because of the different thermal environments that are experienced by the central portion of the wafer compared to the edge portion. More specifically, the temperature gradient generally is higher at the wafer edge compared to the wafer center, due to thermal characteristics. The pull rate is always constant across the wafer. Therefore, the ratio of V/G generally decreases from the center of the wafer to edge of the wafer in the radial direction. The pull rate and hot zone furnace are designed to maintain the V/G ratio, from the center of the wafer to within a diffusion length of the edge of the wafer, below the critical point defect concentrations that would cause agglomerates, i.e. between the first and second critical ratios. Similar considerations apply in the axial direction. In the axial direction, the temperature gradient generally decreases as more of the ingot is pulled, due to the increased thermal mass of the ingot. Accordingly, as the ingot is pulled, the pull rate generally must be decreased in order to maintain the ratio of V/G between the first and second critical ratios.
Thus, by controlling the pull rate profile to maintain V/G between two critical ratios, semi-pure wafers with a vacancy rich region at the center thereof and a pure region between the vacancy rich region and the wafer edge may be formed. The vacancy rich region may include both vacancy point as well as agglomerate defects, and the pure region includes neither vacancy nor interstitial agglomerates. Alternatively and preferably, pure wafers may be formed that may include point defects but that are free of vacancy agglomerates and interstitial agglomerates.
The first and second critical ratios may be determined empirically or by using simulations. The ratios may be determined empirically by slicing a reference ingot into wafers or by slicing the reference ingot axially. Combinations of empirical and simulation techniques may be used.
In particular, the first critical ratio and the second critical ratio may be empirically determined by pulling a reference ingot from a silicon melt in the hot zone furnace at a pull rate that varies over a range of pull rates. The reference ingot is then sliced into wafers. For semi-pure silicon wafers, a wafer having a predetermined size vacancy rich region and that is also free of interstitial agglomerates is identified. Preferably, a wafer having a smallest vacancy rich region and that is also free of interstitial agglomerates is identified. The first and second critical ratios for semi-pure silicon are calculated from the pull rate of the identified wafer and the position of the identified wafer in the ingot.
In order to determine the first and second critical ratios for pure silicon wafers, the reference ingot is pulled, sliced into wafers, and a wafer that is free of vacancy agglomerates and interstitial agglomerates is identified. The first and second critical ratios for pure silicon are determined from the pull rate of the identified wafer and the position of the identified wafer in the ingot.
The reference ingot is preferably pulled from the silicon melt in the hot zone furnace at a pull rate that varies over a range of pull rates from a first pull rate, to a second pull rate that is lower than the first pull rate, to a third pull rate that is higher than the second pull rate and that may be lower or higher than the first pull rate. The first, second and third pull rates are preferably based upon the desired diameter of ingots and expected V/G ratios. Linear changes in pull rates are preferably used so that the first and second critical ratios can be determined.
In another empirical technique, a reference ingot is pulled from the silicon melt in the hot zone furnace at a pull rate that varies over a range of pull rates. The reference ingot is then axially sliced. For semi-pure wafers, at least one axial position in the axially sliced reference ingot is identified, having a smallest vacancy rich region and that is free of interstitial agglomerates. The first and second critical ratios for semi-pure silicon are then calculated from the pull rate corresponding to the identified axial position in the axially sliced ingot.
In order to form perfect silicon, at least one axial position in an axially sliced reference ingot is identified having no interstitial or vacancy agglomerates. The first and second critical ratios for pure silicon are then calculated from the pull rate of the identified at least one axial position and the location of the identified axial position in the axially sliced ingot.
The first and second critical ratios may also be determined theoretically using simulations. In particular, the first and second critical ratios may be identified from Voronkov""s Theory. A pull rate to radial temperature gradient profile may be determined by simulating operation of a specific hot zone furnace during ingot pulling. A pull rate to axial temperature profile may be determined by simulating operation of the hot zone furnace during ingot pulling. A pull rate profile that maintains the ratio of pull rate to temperature gradient in the ingot above the first critical ratio and below the second critical ratio may then be determined from the simulated pull rate to radial temperature profile and the simulated pull rate to axial temperature profile.
It will also be understood that the first and second critical ratios for pure silicon may be identified in a two step process. First, the first and second critical ratios for semi-pure silicon may be determined empirically and/or theoretically. Then, the hot zone structure may be modified until the first and second critical ratios can be determined empirically and/or theoretically.
The present invention can provide a plurality of similar semi-pure monocrystalline silicon wafers that are manufactured from one silicon ingot. Each of the semi-pure silicon wafers has a vacancy rich region at the center thereof that includes vacancy agglomerates and a pure region between the vacancy rich region and the wafer edge that is free of vacancy agglomerates and interstitial agglomerates. The vacancy rich region of each of the wafers has substantially the same diameter. Preferably, the pure region is at least 36% of the wafer area. More preferably, the pure region is at least 60% of the wafer area.
If the ratio of V/G is controlled even more tightly, the present invention can produce a plurality of pure monocrystalline silicon wafers that are manufactured from one silicon ingot, wherein each of the pure silicon wafers is free of vacancy agglomerates and interstitial agglomerates. Accordingly, by maintaining the ratio of pull rate to temperature gradient at the ingot-melt interface between upper and lower bounds, agglomerate defects can be confined to a vacancy rich region at the center of the wafer or can be eliminated to produce pure silicon wafers.